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low skew, 1:6 crystal-to- lvcmos/lvttl fanout buffer ics83905 data sheet ics83905am revision b july 20, 2009 1 ?2009 integrated device technology, inc. general description the ics83905 is a low skew, 1-to-6 lvcmos / lvttl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from idt. the low impedance lvcmos/lvttl outputs are designed to drive 50 ? series or parallel terminated transmission lines. the effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines. the ics83905 is characterized at full 3.3v, 2.5v, and 1.8v, mixed 3.3v/2.5v, 3.3v/1.8v and 2.5v/1.8v output operating supply mode. guaranteed output and part-to-part skew characteristics along with the 1.8v output capabilities makes the ics83905 ideal for high performance, single ended applications that also require a limited output voltage. features ? six lvcmos / lvttl outputs ? outputs able to drive 12 series terminated lines ? crystal oscillator interface ? crystal input frequency range: 10mhz to 40mhz ? output skew: 80ps (maximum) ? rms phase jitter @ 25mhz, (100hz ? 1mhz): 0.26ps (typical), v dd = v ddo = 2.5v offset noise power 100hz............... ..-129.7 dbc/hz 1khz ............... ....-144.4 dbc/hz 10khz ....... ..........-147.3 dbc/hz 100khz ...............-157.3 dbc/hz ? 5v tolerant enable inputs ? synchronous output enables ? operating power supply modes: full 3.3v, 2.5v, 1.8v mixed 3.3v core/2.5v output operating supply mixed 3.3v core/1.8v output operating supply mixed 2.5v core/1.8v output operating supply ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s 6 7 8 9 10 19 20 18 17 16 1 2 3 4 5 13 14 15 12 11 gnd v ddo gnd bclk0 bclk1 bclk4 bclk5 v ddo gnd gnd v dd bclk2 gnd gnd bclk3 enable1 enable2 xtal_in xtal_ou t nc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 xtal_in enable1 bclk5 v ddo bclk4 gnd bclk3 v dd bclk2 gnd bclk1 v ddo bclk0 gnd enable2 xtal_out synchronize synchronize bclk0 bclk1 bclk2 bclk3 bclk4 bclk5 xtal_in xtal_out enable 1 enable 2 ics83905 16-lead soic, 150 mil 3.9mm x 9.9mm x 1.38mm package body m package top view 16-lead tssop 4.4mm x 5.0mm x 0.925mm package body g package top view pin assignments block diagram ics83905 20-lead vfqfn 4mm x 4mm x 0.925mm package body k package top view
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 2 ?2009 integrated device technology, inc. table 1. pin descriptions table 2. pin characteristics function table table 3. clock enable function table figure 1. enable timing diagram name type description xtal_out output crystal oscillator interface. xtal_out is the output. xtal_in input crystal oscillator interface. xtal_in is the input. enable1, enable2 input clock enable. lvcmos /lvttl interface levels. see table 3. bclk0, bclk1, bclk2, bclk3, bclk4, bclk5 output clock outputs. lvcmos /lvttl interface levels. gnd power power supply ground. v dd power power supply pin. v ddo power output supply pin. nc unused no connect. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf c pd power dissipation capacitance (per output) v ddo = 3.465v 19 pf v ddo = 2.625v 18 pf v ddo = 2.0v 16 pf r out output impedance v ddo = 3.3v 5% 7 ? v ddo = 2.5v 5% 7 ? v ddo = 1.8v 0.2v 10 ? control inputs outputs enable 1 enable2 bclk[0:4] bclk5 00low low 0 1 low toggling 1 0 toggling low 1 1 toggling toggling bclk5 bclk0:4 enable2 enable1
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 3 ?2009 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c table 4b. power supply dc characteristics, v dd = v ddo = 2.5v 5%, t a = 0c to 70c table 4c. power supply dc characteristics, v dd = v ddo = 1.8v 0.2v, t a = 0c to 70c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 16 lead soic package 16 lead tssop package 20 lead vfqfn package 78.8 c/w (0 mps) 100.3 c/w (0 mps) 57.5 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current enable [1:2] = 00 10 ma i ddo output supply current enable [1:2] = 00 5 ma symbol parameter test conditions minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current enable [1:2] = 00 8 ma i ddo output supply current enable [1:2] = 00 4 ma symbol parameter test conditions minimum typical maximum units v dd power supply voltage 1.6 1.8 2.0 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current enable [1:2] = 00 5 ma i ddo output supply current enable [1:2] = 00 3 ma
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 4 ?2009 integrated device technology, inc. table 4d. power supply dc characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = 0c to 70c table 4e. power supply dc characteristics, 3.3v 5%, v ddo = 1.8v 0.2v%, t a = 0c to 70c table 4f. power supply dc characteristics, v dd = 2.5v 5%, v ddo = 1.8v 0.2v%, t a = 0c to 70c symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current enable [1:2] = 00 10 ma i ddo output supply current enable [1:2] = 00 4 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current enable [1:2] = 00 10 ma i ddo output supply current enable [1:2] = 00 3 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current enable [1:2] = 00 8 ma i ddo output supply current enable [1:2] = 00 3 ma
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 5 ?2009 integrated device technology, inc. table 4g. lvcmos/lvttl dc characteristics, t a = 0c to 70c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information, output load test circuit diagrams. table 5. crystal characteristics symbol parameter test conditi ons minimum typical maximum units v ih input high voltage enable1, enable2 v dd = 3.3v 5% 2 v dd + 0.3 v v dd = 2.5v 5% 1.7 v dd + 0.3 v v dd = 1.8v 0.2v 0.65 * v dd v dd + 0.3 v v il input low voltage enable1, enable2 v dd = 3.3v 5% -0.3 0.8 v v dd = 2.5v 5% -0.3 0.7 v v dd = 1.8v 0.2v -0.3 0.35 * v dd v v oh output high voltage v ddo = 3.3v 5%; note 1 2.6 v v ddo = 2.5v 5%; i oh = -1ma 2.0 v v ddo = 2.5v 5%; note 1 1.8 v v ddo = 1.8v 0.2v; note 1 v ddo - 0.3 v ol output low voltage; note 1 v ddo = 3.3v 5%; note 1 0.5 v v ddo = 2.5v 5%; i ol = 1ma 0.4 v v ddo = 2.5v 5%; note 1 0.45 v v ddo = 1.8v 0.2v; note 1 0.35 parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 10 40 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf drive level 1mw
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 6 ?2009 integrated device technology, inc. ac electrical characteristics table 6a. ac characteristics, v dd = v ddo = 3.3v 5%,t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven relative to a signal a crystal would provide. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: see phase noise plot. note 5: these parameters are guaranteed by characterization. not tested in production. table 6b. ac characteristics, v dd = v ddo = 2.5v 5%,t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven relative to a signal a crystal would provide. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: see phase noise plot. note 5: these parameters are guaranteed by characterization. not tested in production. symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit(?) rms phase jitter (random); note 4 25mhz, integration range: 100hz ? 1mhz 0.13 ps t r / t f output rise/fall time 20% to 80% 200 800 ps odc output duty cycle 48 52 % t en output enable time; note 5 enable1 4 cycles enable2 4 cycles t dis output disable time; note 5 enable1 4 cycles enable2 4 cycles symbol parameter test conditions minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit rms phase jitter (random); note 4 25mhz, integration range: 100hz ? 1mhz 0.26 ps t r / t f output rise/fall time 20% to 80% 200 800 ps odc output duty cycle 47 53 % t en output enable time; note 5 enable1 4 cycles enable2 4 cycles t dis output disable time; note 5 enable1 4 cycles enable2 4 cycles
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 7 ?2009 integrated device technology, inc. table 6c. ac characteristics, v dd = v ddo = 1.8v 0.2v,t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven relative to a signal a crystal would provide. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65.. note 4: these parameters are guaranteed by characterization. not tested in production. table 6d. ac characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%,t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven relative to a signal a crystal would provide. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by characterization. not tested in production. symbol parameter test conditions minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit(?) rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.27 ps t r / t f output rise/fall time 20% to 80% 200 900 ps odc output duty cycle 47 53 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles symbol parameter test conditions minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.14 ps t r / t f output rise/fall time 20% to 80% 48 52 ps odc output duty cycle 200 800 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 8 ?2009 integrated device technology, inc. table 6e. ac characteristics, v dd = 3.3v 5%, v ddo = 1.8v 0.2v,t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow grea ter than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven relative to a signal a crystal would provide. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65.. note 4: these parameters are guaranteed by characterization. not tested in production. table 6f. ac characteristics, v dd = 2.5v 5%, v ddo = 1.8v 0.2v, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow grea ter than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven relative to a signal a crystal would provide. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by characterization. not tested in production. symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.18 ps t r / t f output rise/fall time 20% to 80% 200 900 ps odc output duty cycle 48 52 % t en output enable time; note 4 enable1 4 cycles enable2 cycles t dis output disable time; note 4 enable1 4 cycles enable2 cycles symbol parameter test conditions minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.19 ps t r / t f output rise/fall time 20% to 80% 200 900 ps odc output duty cycle 47 53 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 9 ?2009 integrated device technology, inc. typical phase noise at 25mhz (2.5v core/2.5v output) typical phase noise at 25mhz (3.3vcore/3.3v output) raw phase noise data ? 25mhz rms phase jitter (random) 100hz to 1mhz = 0.26ps (typical) noise power dbc hz offset frequency (hz) raw phase noise data ? .25mhz rms phase jitter (random) 100hz to 1mhz = 0.13ps (typical) noise power dbc hz offset frequency (hz)
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 10 ?2009 integrated device technology, inc. parameter measureme nt information 3.3v core/3.3v lvcmos output load ac test circuit 1.8v core/1.8v lvcmos output load ac test circuit 3.31.8v core/1.8v lvcmos output load ac test circuit 2.5v core/2.5v lvcmos output load ac test circuit 3.3v core/2.5v lvcmos output load ac test circuit 2.5v core/1.8v lvcmos output load ac test circuit scope qx lvcmos gnd v dd, -1.65v5% 1.65v5% v ddo scope qx lvcmos gnd v dd, -0.9v0.1v 0.9v0.1v v ddo scope qx lvcmos gnd v dd -0.9v0.1v 2.4v0.9v v ddo 0.9v0.1v scope qx lvcmos gnd v dd, -1.255% 1.25v5% v ddo scope qx lvcmos gnd v dd -1.255% 2.05v5% v ddo 1.25v5% scope qx lvcmos gnd v dd -0.9v0.1v 1.6v0.025% v ddo 0.9v0.1v
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 11 ?2009 integrated device technology, inc. parameter measurement in formation, continued output skew output rise/fall time rms phase jitter output duty cycle/pulse width/period qx qy t sk(b) v cco 2 v cco 2 20% 80% 80% 20% t r t f bclk[0:5] phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power t period t pw t period odc = v dd 2 x 100% t pw bclk[0:5]
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 12 ?2009 integrated device technology, inc. application information crystal input interface figure 2 shows an example of ics83905 crystal interface with a parallel resonant crystal. the frequency accuracy can be fine tuned by adjusting the c1 and c2 values. for a parallel crystal with loading capacitance cl = 18pf, to start wit h, we suggest c1 = 15pf and c2 = 15pf. these values may be slightly fine tuned further to optimize the frequency accuracy for different board layouts. slightly increasing the c1 and c2 values will slightly reduce the frequency. slightly decreasing the c1 and c2 values will slightly increase the frequency. for the oscillator circuit below, r1 can be used, but is not required. for new designs, it is recommended that r1 not be used. figure 2. crystal input interface lvcmos to xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be re duced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configurat ion requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . by overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. figure 3. general diagram for lvcmos driver to xtal input interface xtal_in xtal_out c1 15p c2 15p x1 18pf parallel crystal r1 (optional) 0 xtal_in xtal_out ro rs zo = ro + rs 50 ? 0.1f r1 r2 v cc v cc
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 13 ?2009 integrated device technology, inc. vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos output can be left floating. there should be no trace attached. solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 14 ?2009 integrated device technology, inc. layout guideline figure 5 shows an example of ics83905 applications schematic. in this example, the device is operated at v dd = 3.3v and v ddo = 3.3v. the decoupling capacitors should be loacted as close as possible to the power pins. the input is driven by an 18pf load resonant quartz crystal. the tuning capacitors (c1, c2) are fairly accurate, but minor adjustments might be required. for the lvcmos output drivers, two termination examples are shown in the schematic. for additonal termination, examples are shown in the lvcmos termination applications note. figure 5. schmatic of recommended layout vdd r2 31 c6 .1uf vddo enable 2 r4 100 zo = 50 ohm vdd = 3.3v c2 15pf vdd c1 15pf lvcmos enable 1 cl = 18 pf optional termination r3 100 c4 .1uf lvcmos zo = 50 ohm vddo u1 ics83905i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 xtal_out enable 2 gnd bclk0 vddo bclk1 gnd bclk2 vdd bclk3 gnd bclk4 vddo bclk5 enable 1 xta l _ i n c3 10uf vddo = 3.3v unused outputs can be left floating. there should be no trace attached to unused outputs. device characterized and specification limits set with all outputs terminated. c5 .1uf
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 15 ?2009 integrated device technology, inc. power considerations this section provides information on power dissipa tion and junction temperature for the ics83905. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics83905 is the sum of the core power plus the analog power plus the power dissipated in th e load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * (i dd + i ddo ) = 3.465v *(10ma + 5ma) = 51.9mw output impedance r out power dissipation due to loading 50 ? to v dd /2 output current i out = v dd_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 7 ? )] = 30.4ma power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 7 ? * (30.4ma) 2 = 6.5mw per output total power dissipation on the r out total power (r out ) = 6.5mw * 6 = 39mw dynamic power dissipation at 25mhz power (25mhz) = c pd * frequency * (v dd ) 2 = 19pf * 25mhz * (3.465v) 2 = 5.70mw per output total power (25mhz) = 5.70mw * 6 = 34.2mw total power dissipation total power = power (core) max + total power (r out ) + total power (25mhz) = 51.98mw + 39mw + 34.2mw = 125.1mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 100.3c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.125w *100.3c/w = 82.5c. th is is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ja for 16 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 100.3c/w 96.0c/w 93.9c/w
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 16 ?2009 integrated device technology, inc. reliability information table 8a. ja vs. air flow table for a 16 lead tssop table 8b. ja vs. air flow table for a 16 lead soic table 8c. ja vs. air flow table for a 20 lead vfqfn transistor count the transistor count for ics83905: 339 pin compatible to mpc905 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 78.8c/w 71.1c/w 66.2c/w ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 57.5c/w 50.3c/w 45.1c/w
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 17 ?2009 integrated device technology, inc. package outline and package dimensions package outline - g suffix for 16 lead tssop table 9a. package dimensions for 16 lead tssop reference document: jedec publication 95, mo-153 package outline - m suffix for 16 lead soic table 9b. package dimensions for 16 lead soic reference document: jedec publication 95, ms-012 all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10 all dimensions in millimeters symbol minimum maximum n 16 a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 9.80 10.00 e 3.80 4.00 e 1.27 basic h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 0 8
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 18 ?2009 integrated device technology, inc. package outline and package dimensions package outline - k suffix for 32 lead vfqfn note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 9c below. table 9c. package dimensions reference document: jede c publication 95, mo-220 to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or jedec variation: vggd-1/-5 all dimensions in millimeters symbol minimum nominal maximum n 20 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.30 n d & n e 5 d & e 4.00 basic d2 & e2 1.95 2.25 e 0.50 basic l 0.35 0.75
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 19 ?2009 integrated device technology, inc. ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 83905am 83905am 16 lead soic tube 0 c to 70 c 83905amt 83905am 16 lead soic 2500 tape & reel 0 c to 70 c 83905amlf 83905aml ?lead-free? 16 lead soic tube 0 c to 70 c 83905amlft 83905aml ?lead-free? 16 lead soic 2500 tape & reel 0 c to 70 c 83905AG 83905AG 16 lead tssop tube 0 c to 70 c 83905AGt 83905AG 16 lead tssop 2500 tape & reel 0 c to 70 c 83905AGlf 83905AGl ?lead-free? 16 lead tssop tube 0 c to 70 c 83905AGlft 83905AGl ?lead-free? 16 lead tssop 2500 tape & reel 0 c to 70 c 83905ak 83905a 20 lead vfqfn tray 0 c to 70 c 83905akt 83905a 20 lead vfqfn 2500 tape & reel 0 c to 70 c 83905aklf 3905al ?lead-free? 20 lead vfqfn tray 0 c to 70 c 83905aklft 3905al ?lead-free? 20 lead vfqfn 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer ics83905am revision b july 20, 2009 20 ?2009 integrated device technology, inc. revision history sheet rev table page description of change date a 2 added enable timing diagram. 3/28/05 bt6a - t6f 1 5 - 7 8 features section - added rms phase jitter bullet. ac characteristics tables - added rms phase jitter specs. added phase noise plot. 4/8/05 b t9 14 ordering information table - added tssop, non-lf part number. 4/25/05 b 11 12 added crystal input interfac e in application section. added schematic layout. 5/16/05 b 3 11 13 absolute maximum ratings - corrected 20 lead vfqfn package thermal impedance. added recommendations for unused input and output pins. corrected theta ja air flow table for 20 lead vfqfn. 10/2/06 b t9 11 12 17 added lvcmos to xtal interface section. added thermal release path section. ac characteristics table - added lead-free marking for 20 lead vfqfn package. 7/9/07 b t7b - t7c 3 12 14 16 absolute maximum ratings - updated tssop and vfqfn thermal impedance. updated thermal release path section. updated tssop and vfqf n thermal impedance. added note to vfqfn package outline. 1/24/08 b 15 added power considerations section. converted datasheet format. 7/20/09
ics83905 data sheet low skew, 1:6 crystal-to-lvcmos/lvttl fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2009. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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